en.radzio.dxp.pl

STM32 FSMC to Avalon bus wrapper
This wrapper converts STM32 FSMC interface signals (multiplexed) to Altera Avalon bus signals. It provide access to SOPC Builder/QSYS system peripherals from STM32 microcontroller.

FSMC to Avalon wrapper

Using this wrapper with QSYS SDRAM controller make easy way to use SDRAM memory with STM32 microcontroller (at this moment STM32 uC don't have SDRAM controller).

Source code (VHDL) of wrapper

--=================================================================================================
-- STM32 FSMC to AVALON bus wrapper
--=================================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
--=================================================================================================
-- Entity
--=================================================================================================
entity avalon_wrapper is
PORT(
  CLK                : in std_logic;
  RESET              : in std_logic;

  HOST_DATAIN        : in std_logic_vector (15 downto 0);
  HOST_DATAOUT       : out std_logic_vector (15 downto 0);
  HOST_DATAEN        : out std_logic;
  HOST_NRD           : in STD_LOGIC;
  HOST_NWR           : in STD_LOGIC;
  HOST_NCS           : in STD_LOGIC;
  HOST_NBL0          : in STD_LOGIC;
  HOST_NBL1          : in STD_LOGIC;
  HOST_NADV          : in STD_LOGIC;
  HOST_NWAIT         : out STD_LOGIC;

  AVALON_WRITEDATA   : out std_logic_vector (31 downto 0);
  AVALON_READDATA    : in std_logic_vector (31 downto 0);
  AVALON_ADDRESS     : out std_logic_vector (31 downto 0);
  AVALON_WRITE_N     : out std_logic;
  AVALON_READ_N      : out std_logic;
  AVALON_WAITREQUEST : in std_logic;
  AVALON_BYTEENABLE : out std_logic_vector(1 downto 0));
end avalon_wrapper;
--=================================================================================================
-- Architechture
--=================================================================================================
architecture wrapper of avalon_wrapper is

signal address : std_logic_vector(31 downto 0);
signal data : std_logic_vector(31 downto 0);

begin

demux : process (CLK, RESET)
begin
  if(RESET = '1') then
    address <= X"00000000";
    data <= X"00000000";
  elsif rising_edge(CLK) then
    if(HOST_NADV = '0') then
      address(16 downto 1) <= HOST_DATAIN;
    else
      data(15 downto 0) <= HOST_DATAIN;
    end if;
  end if;
end process;

AVALON_WRITEDATA   <= data when HOST_NCS = '0' else (others => '0');
AVALON_ADDRESS     <= address when HOST_NCS = '0' else (others => '0');
AVALON_WRITE_N     <= HOST_NWR or HOST_NCS;
AVALON_READ_N      <= HOST_NRD or HOST_NCS;

AVALON_BYTEENABLE(0) <= not HOST_NBL0;
AVALON_BYTEENABLE(1) <= not HOST_NBL1;

HOST_DATAOUT <= AVALON_READDATA(15 downto 0);
HOST_DATAEN <= (not HOST_NRD) and (not HOST_NCS);

HOST_NWAIT <= AVALON_WAITREQUEST when (((HOST_NWR xor HOST_NRD) = '1') and (HOST_NCS = '0')) else '0';
end wrapper;
--=================================================================================================
-- End of file
--=================================================================================================